The present invention relates to a Thin Film Transistor Liquid Crystal Display (TFT-LCD) driving circuit.
A schematic structural diagram of a TFT-LCD driving circuit in the prior art is as shown in FIG. 1. A timing controller 1 is used to generate various control signals, such as a gate line sync signal (generally referred to as CPV (Clock Pulse Vertical) signal in the art), a gate line start signal (generally referred to as STV (Start Vertical) signal in the art), a gate line output control signal (generally referred to as OE1 (Output Enable) signal in the art), and a signal (generally referred to as OE2 signal in the art) required by a Multi Level Gateway (MLG) gate driving signal. The timing controller 1 inputs the generated various control signals into a High Voltage TFT-LCD Logic Driver 2, which generates a first clock signal (generally referred to as CLK signal in the art), a second clock signal (generally referred to as CLKB signal in the art), and an improved STV signal (generally referred to as STVP signal in the art) from the CPV signal, the STV signal, the OE1 signal, the OE2 signal, and so on. The improved STV signal refers to a STV signal whose level has been adjusted, because the level of the STV signal output from the timing controller may be not consistent with that of a STV signal required by a gate driving circuit, and the level of the STV signal output from the timing controller has to be converted by some level conversion circuits. The CLKB signal, the CLK signal and the STVP signal are input to the gate driving circuit, thus the gate lines may be driven to operate.
A timing diagram for a TFT-LCD driving circuit in the prior art is as shown in FIG. 2a, which shows a timing relationship between the STV signal, the CPV signal, the OE1 signal and the OE2 signal and gate driving signals output by the gate driving circuit (FIG. 2a only shows two gate driving signals, GATE1 and GATE2, which are gate driving signals respectively used to drive a first row of gate lines and a second row of gate lines).
A timing diagram for another TFT-LCD driving circuit in the prior art is as shown in FIG. 2b, which shows a timing relationship between the STV signal, the CPV signal and the OE2 signal and gate driving signals output by the gate driving circuit (FIG. 2b only shows two gate driving signals, GATE1 and GATE2, which are gate driving signals respectively used to drive a first row of gate lines and a second row of gate lines).
Differences between FIG. 2a and FIG. 2b lie in that in FIG. 2a, the OE1 signal is used, and the gate driving signals are started to be output from falling edges of the OE1 signal; whereas in FIG. 2b, the OE1 signal is not used, and the gate driving signals are started to be output from falling edges of the OE2 signal.
In the TFT-LCD driving circuit, generally, when the gate driving circuit outputs a gate driving signal for turning on a row of gate lines, a source driving circuit inputs data signals for respective pixels to which the row of gate lines correspond into respective pixel electrodes of the row. A schematic diagram of an ideal timing relationship between gate driving signals of a TFT-LCD and data signals input by a source driving circuit in the prior art is as shown in FIG. 3. When the gate driving signals are at a high level, the source driving circuit inputs the data signals into pixel electrodes.
FIG. 3 shows the ideal timing relationship. However, in actual applications, both rising edges and falling edges of the gate driving signals have certain time delays. A schematic diagram of an actual timing relationship between gate driving signals of a TFT-LCD and data signals input by a source driving circuit in the prior art is as shown in FIG. 4. If the time delays of the gate driving signals are relatively significant, the gate driving signal GATE2 for the second row has started to rise when the gate driving signal GATE1 for the first row is just at a falling edge, then the source driving circuit has already input data to which a second row of pixels correspond while respective TFTs to which the first row of gate lines correspond are not yet turned off, thus the data input to a first row of pixels are confused, and thereby affecting picture display.
For a Gate Driver on Array (GOA) panel, electrons in TFTs therein have a low moving speed, and the data confusion caused by the delays of the gate driving signals will be more severe.